While testing the design, the capacity of the state preservation registers to keep hold of their state needs to be verified when the power domain is powered off. Isolation cells are located at the limit of two power domains keeping in mind to isolate the power-on and power-off domains. Based upon the operating conditions, different power domain blocks are subject to different supply voltages and each power domain block is connected to other power domain block with the help of level shifters.
Once the scan synthesis starts, the functional flops are replaced by their scan equivalent flops. This guarantees that every power domain is having dedicated scan chains which are active in the power domain that is ON. In order to minimize power dissipation, particularly leakage power dissipation caused by the shrinking power technologies, power switches are generally employed in modern low-power design circuits. One or more power switches are equipped at different parts of the design to facilitate the functionality of power gating.
In the current implementation in this paper, for the low-power DFT, we have adjusted the frequency of the scan clock in such a way that it meets the design specification and also directly resulted in reducing the power consumption in the circuit. The input design is a phase-locked loop PLL with multiple clocks.
Low-power design-for-test implementation on phase-locked loop design
A simple PLL design looks as shown in Figure 3. PLL is a circuit that can be used for high-frequency application and very short interlocking time. PLL is a feedback system that detects the phase error and then adjusts the phase of the output. The phase error detector detects phase error between the output and the input through the feedback system.
The digital controlled oscillator DCO adjusts the phase difference. One of the primary applications of PLL is in carrier synchronization and bit synchronization systems to improve their synchronization properties. Another important application of PLL is its use as a frequency synthesizer.
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The gate-level netlist is taken as the input for performing the DFT process and implementing the low-power DFT technique of decreasing the scan clock frequency and dividing it into multiple power domains. Here the emphasis is on reducing the dynamic power. The general representation of CMOS complementary metal-oxide semiconductor logic gate for switching power calculation is shown in Figure 4. The transition rate of the nodes can be slower than the clock rate. As we can see from equation 4 , power is directly proportional to the clock frequency. Hence, reducing the clock frequency such that it falls between the specification ranges, the power can be reduced without affecting the timing violations.
The results of this experiment at the scan synthesis level after varying the clock frequency are tabulated in Table 1. Table 1. These results have been obtained for the PLL design netlist. The above results have been generated with the help of the Synopsys DC tool. Cell internal power is the power dissipated within the boundary of a cell.
During switching, a circuit dissipates the internal power by charging or discharging of any existing capacitances internal to the cell.
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Net switching power occurs when signals which go through the CMOS circuits change their logic state. At this moment, energy is drawn from the power supply to charge up the output node capacitance. Synopsys DC is a synthesis tool that takes the design netlist as the input and reports the area, power, and so on consumed by the chip. There are no simulations carried out by the authors as they are not considering the functionality of the PLL netlist or the asynchronous first-in first-out FIFO netlist used.
They are only taking the netlist as the input and carrying out the low-power DFT technique research on the inputs provided by the designer. Hence, there are no simulation reports shown in the results. The results of this experiment at the scan synthesis level after varying the clock frequency are tabulated in Table 2. Table 2. Comparison table showing the power values before and after applying the low-power technique for asynchronous FIFO. These results have been obtained for the asynchronous FIFO design netlist.
This is the reduction technique for dynamic power which is also the switching power in any SoC. Figure 6. Asynchronous FIFO graphical representation of power comparison.
All these results have been calibrated by ensuring that there are no setup or hold violations in the circuit after varying the clock frequency. It is clearly proved from equation 3 that power is directly proportional to frequency. One of the techniques which will be applied in the further version of the paper will be dividing the scan clock for even and odd chains and thereby reducing the power consumption in the scan chain.
Reducing the scan clock frequency does not affect either the functionality or the performance of the IC. The scan clock frequency is used only for the purpose of DFT and it is not going to be used as the functional clock. Hence, any change in the scan clock frequency will not affect either the functionality or the performance of the IC.
I would also like to thank the management of K L University for giving me this opportunity to conduct the experiment and using their lab premises. Skip to main content. Measurement and Control. Article Menu. Download PDF. Open EPUB.
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Article Information Volume: 52 issue: , page s : This article is distributed under the terms of the Creative Commons Attribution 4. Keywords Design for test , low power , unified power format , common power format , scan , clock gating circuitry , automatic test pattern generation , synthesis , phase-locked loop , asynchronous first-in first-out. DFT flow diagram. Open in new tab.
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Scan synthesis phase. Figure 2. Scan synthesis flow chart. Low-power specification formats. Low-power DFT techniques. Clock gating circuitry. Power domains. Low-power cell. Multiple supply voltages. Power-aware DFT.